1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device having a multilayer gate structure including a floating gate and a control gate.
2. Description of the Related Art
FIGS. 1 through 3 illustrates a known NAND type EEPROM realized by utilizing shallow trench isolation (STI). FIG. 1 is a schematic plan view and FIGS. 2 and 3 are two different cross-sectional views of FIG. 1.
As shown in FIG. 2, a gate insulation film GI, which is a tunneling insulation film, is formed on a silicon substrate (Si-sub) and floating gates FG are formed thereon. The floating gates FG of adjacent cells are separated and electrically insulated from each other. The structure that separates adjacently located floating gates FG apart from each other is referred to as a slit. The floating gates FG between a pair of slits are covered at the top and the opposite lateral sides by an inter-gate insulation film IGI. Each floating gate FG can be made to hold an electric charge for a long period because it is covered by a tunneling insulation film and an inter-gate insulation film.
A control gate CG is formed on the inter-gate insulation film. Normally, a control gate CG is shared by a large number of cell transistors and adapted to drive the number of cell transistors simultaneously. The control gate CG is also referred to as word line WL.
On the other hand, the cross-sectional view of FIG. 3 is taken along a bit line BL. Stacked gate structures illustrated in FIG. 3 are arranged on the substrate in rows along the direction of bit lines BL. Each cell transistor is processed in a self-aligning manner by means of resist or a processing mask layer. In the NAND type memory device where a number of cells are connected in series by way of select gates, adjacent cells share a source and a drain in order to reduce the area occupied by each cell. Each word line WL and the gap separating adjacent word lines WL are formed with minimum feature size by micro-processing.
Electrons are injected into a floating gate FG by applying a high write potential to the corresponding control gate CG and grounding the substrate. As cell transistors are micronized, an increased parasitic capacitance appears between adjacent cells and between a floating gate FG and a peripheral structure. For this reason, there is a tendency of raising the write voltage of cell transistors for the purpose of increasing the data writing rate. Control gates CG need to be reliably insulated from each other and word line drive circuits are required to withstand high voltages when a high voltage is used for the write voltage. This poses a problem when arranging memory elements at high density and driving them to operate at high speed.
It is possible to roughly estimate the potential required for write operation by seeing the structure shown in FIGS. 1 and 3. The control gate CG and the floating gate FG and the floating gate FG and the substrate can be regarded as capacitors where the gate insulation film and the tunneling insulation film are respectively sandwiched. In other words, as seen from the control gate CG, the memory cell is equivalent to a structure where two capacitors are connected in series.
FIG. 4 is an equivalent circuit diagram of a cell that is obtained when the capacitance of the capacitor between the control gate CG and the floating gate FG is Cip and the capacitance of the capacitor between the floating gate FG and the substrate is Ctox. The electric potential Vfg of the floating gate FG when a high write potential (Vpgm=Vcg) is applied to the control gate CG is defined by Cip and Ctox and can be roughly estimated by using the formula below:Vfg=Cr×(Vcg−Vt+Vt0),where Cr=Cip/(Cip+Ctox) and Vt represents the threshold voltage of the cell transistor while Vt0 represents the threshold voltage (neutral threshold voltage) when the floating gate FG is totally free from electric charge.
The higher the electric potential Vfg of the floating gate FG, the stronger the electric field applied to the tunneling insulation film so injection of electrons into the floating gate FG can easily take place. It will be appreciated from the above formula that the value of Vfg can be raised by increasing the capacitance ratio (Cr) provided that Vcg is held to a constant level. In other words, it is necessary to make Cip have a large value relative to Ctox in order to reduce the write voltage.
The capacitance of a capacitor is proportional to the dielectric constant of the thin film arranged between the electrodes and the area of the opposed electrodes and inversely proportional to the distance between the opposed electrodes. A write/erase operation is obstructed when a leak current flows through the tunneling insulation film for allowing an electric charge to pass through for the purpose of the write/erase operation. Therefore, a technique of increasing the contact area of the gate insulation film and the floating gate FG and that of the gate insulation film and the control gate CG is normally used to increase the value of Cip. Techniques such as increasing the top surface of the floating gate FG by reducing the width of the slit (dimension 1a in FIG. 2) and increasing the length of the lateral walls of the floating gate FG (dimension 1b in FIG. 2) by increasing the film thickness of the floating gate FG have been developed to date.
However, when such a technique is used, the slit needs to be extremely micronized relative to the dimensions of the gate and the wiring materials and the difficulty of forming the gate increases as the floating gate FG is made thicker. Additionally, the parasitic capacitance between FG-FG increases as a result of micronization. In short, it obstructs micronization of cell transistors to maintain the capacitance ratio.
It is conceivable to reduce the write voltage by modifying the configuration of the floating gate FG and the control gate CG.
As a matter of fact, Japanese Laid-Open Patent (Kokai) No. 11-145429 describes a NAND type EEPROM that is designed to allow write/erase/read operations to be performed with a low voltage by increasing the capacitance between booster plates.
Japanese Laid-Open Patent (Kokai) No. 2002-217318 describes a nonvolatile memory device including micronized elements that are realized by raising the coupling ratio of the floating gate and the control gate and thereby reducing the write voltage.
Japanese Laid-Open Patent (Kokai) No. 2002-50703 describes a nonvolatile semiconductor memory device including MOSFETs that show improved write/erase/read characteristics and area realized by forming floating gate at opposite lateral sides of each control gate.
Furthermore, Y. Sasago et al. “10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology” 2002 IEEE IEDM, pp. 952-954 describes an AG-AND memory cell where an assist gate is arranged adjacent to a floating gate.
However, it is still difficult to increase the capacitance between the control gate and the floating gate by means of the above described prior art. In other words, it is difficult to reduce the write voltage and realize a highly integrated memory that operates at high speed by means of the prior art. Therefore, nonvolatile semiconductor memory devices that can reduce the write voltage, has high capacity and realize a high speed operation.
Furthermore, in the prior art, a selection gate of a selection transistor for selecting a memory cell is constituted by electrically connecting a control gate to a floating gate positioned in an end portion.
When a memory cell transistor and the selection transistor are formed in a two-layer gate structure, for the micronizing of the memory cell, a height of a gate electrode needs to be increased in order to maintain a coupling capacitance equal to that before micronization. Therefore, in this structure, the height of the gate electrode of the selection transistor also increases, thus it becomes difficult to process the gate electrode.
Moreover, since the selection transistor requires superior cut-off characteristics as compared with the memory cell transistor, the selection transistor is formed in such a manner that a channel length is sufficiently large as compared with the memory cell transistor. Thereafter, by the forming of the selection transistor, periodicity of the memory cell largely collapses, and it becomes difficult to adjust the channel lengths of the memory cells positioned on opposite ends of a memory cell array. Furthermore, a problem occurs that a margin of lithography of the memory cell array drops.